Miniatuarization and high integration of nonvolatile memories with their floating gates introduced into gate insulator film multilayer structures of MOS transistors are easy, because of their simple structure. Thus, the nonvolatile memory becomes a standard nonvolatile memory cell structure in a silicon integrated circuit. Flash memories, in particular, which have enabled electrical bulk erasing, are suitable for implementation of small-sized, large-capacity nonvolatile semiconductor memory devices. Thus, taking the flash memory as the memory that is essential for portable information devices, development efforts toward a larger capacity, a higher operating speed, lower power consumption, and higher reliability of the flash memory are continued.
Generally, the MOS transistor gate multilayer structure of a flash memory cell includes two types of conductive layers: a floating gate and a control gate, formed of a poly silicon film. Further, an inter-poly insulator film that separates these two types of conductive layers and a tunnel dielectric are disposed. The tunnel dielectric separates the floating gate from the surface of a silicon substrate below which an MOS transistor channel is formed. Thus, functionally, the multilayer structure is of the four-layer structure in which two types of insulator layers and two types of conductive layers are laminated. In terms of an equivalent circuit, the multilayer structure is of the structure in which a capacitor C1 formed of the control gate, inter-poly insulator film, and floating gate is connected in series with a capacitor C2 formed of the floating gate, tunnel dielectric, and channel.
A control gate voltage necessary for forming the channel of the MOS transistor differs according to the presence or absence of electrical charge stored in the floating gate, which is used for information memory device in this memory cell. Electrical charge injection into the floating gate is implemented by applying a comparatively high voltage to the control gate, thereby causing the electrical charge to flow into the floating gate through the tunnel dielectric capacitor C2 from the surface of the silicon substrate. The tunnel dielectric capacitor C2 needs to meet a requirement that the electrical charge be passed through, which is extremely severe in view of reliability of the insulator film, and because of the need for having the property of not letting the electrical charge stored in the floating gate escape during an information holding operation, a silicon dioxide film is generally employed. If injected electrical charge leaks out to the control gate through the inter-poly insulator capacitor C1 during an operation of electrical charge injection into the floating gate, the injection cannot be efficiently performed. For this reason, a capacitor structure in which leakage current is small even if a high electrical field is applied is generally adopted for the inter-poly insulator capacitor C1. Generally, a so-called ONO structure in which a silicon nitride film is sandwiched between silicon dioxide films is employed for the inter-poly insulator film.
On the other hand, in order to efficiently perform electrical charge injection into the floating gate, it is important to apply the control gate voltage on the serious structure of C1 and C2 to the tunnel dielectric capacitor C2 as much as possible. By enhancing this efficiency, high-speed information memory device becomes possible. In order to achieve this, it is desirable that the capacity of C1 should be larger than the capacity of C2 as much as possible. This corresponds to reduction in the thickness of the inter-poly insulator film constituting C1 as much as possible. However, for the reason described before, C1 must have small leakage current even if a high electrical field is applied thereto. How to solve these two contradictory technical problems is the most important challenge for the inter-poly insulator film of the flash memory.
The ONO structure that is in most wide use, for example, is a technique most widely used for this challenge. The silicon nitride film has a dielectric constant twice as large as the silicon dioxide film, and can reduce the leakage current. A technique for employing alumina or tantalum pentoxide is likewise proposed as the technique that uses the insulator film having a high dielectric constant. This is discussed on pp. 117–118 of 1997 Symposium on VLSI Technology Digest of Technical Papers (1997). On the other hand, a technique for adding zirconium or silicon to alumina, thereby obtaining the same effect is discussed on pp. 605–608 of 1998 International Electron Device Meeting (IEDM) Technical Digest (1998).
If a tantalum pentoxide film, in particular, is employed, its dielectric constant, which is about seven times that of the silicon dioxide film can be used. Thus, the effect becomes large. A structure in which the tantalum pentoxide film is laminated onto the silicon dioxide film or the silicon oxynitride film or a structure in which the tantalum pentoxide film is sandwiched by the silicon dioxide films is known. JP-A-2000-195856, JP-A-2000-49241, JP-A-11-260938, and JP-A-2001-15714, for example, can be pointed out as describing the structure of this type.